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(parent: dd0b162) | patch
drm/amd/display: update dispclk and dppclk vco frequency
authorEric Yang <Eric.Yang2@amd.com>
Fri, 15 Nov 2019 17:04:25 +0000 (12:04 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 5 Dec 2019 23:23:04 +0000 (18:23 -0500)
commit44ce6c3dc8479bb3ed68df13b502b0901675e7d6
tree45979ce66d0ea9908ce127875dd62ff3e61d781btree | snapshot
parentdd0b162fd00915728860a360c97752988782b8cccommit | diff
drm/amd/display: update dispclk and dppclk vco frequency

Value obtained from DV is not allowing 8k60 CTA mode with DSC to
pass, after checking real value being used in hw, find out that
correct value is 3600, which will allow that mode.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c diff | blob | history
Domain: System / Kernel;