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author	Egor Chesakov <Egor.Chesakov@microsoft.com>
	Fri, 1 May 2020 23:30:22 +0000 (16:30 -0700)
committer	GitHub <noreply@github.com>
	Fri, 1 May 2020 23:30:22 +0000 (16:30 -0700)
commit	44a331315ec3c8ecab9e6a6fd25dff7d0ee8036e
tree	60484a5ffb6ead2d282c1757a0789c8e2512a85e	tree \| snapshot
parent	87f391001eca716a8db896f5c3855d33fe30aca8	commit \| diff

[Arm64] Fix JIT/HardwareIntrinsics/Arm/AdvSimd tests (#35726)

* Set LargestVectorSize to 16 where it must be in GenerateTests.csx

* Update AdvSimd/

67 files changed:

src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLower.Vector64.Byte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLower.Vector64.Int16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLower.Vector64.Int32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLower.Vector64.SByte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLower.Vector64.UInt16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLower.Vector64.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLowerAndAdd.Vector64.Byte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLowerAndAdd.Vector64.Int16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLowerAndAdd.Vector64.Int32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLowerAndAdd.Vector64.SByte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLowerAndAdd.Vector64.UInt16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AbsoluteDifferenceWideningLowerAndAdd.Vector64.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningHighNarrowLower.Vector64.Byte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningHighNarrowLower.Vector64.Int16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningHighNarrowLower.Vector64.Int32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningHighNarrowLower.Vector64.SByte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningHighNarrowLower.Vector64.UInt16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningHighNarrowLower.Vector64.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningRoundedHighNarrowLower.Vector64.Byte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningRoundedHighNarrowLower.Vector64.Int16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningRoundedHighNarrowLower.Vector64.Int32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningRoundedHighNarrowLower.Vector64.SByte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningRoundedHighNarrowLower.Vector64.UInt16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddReturningRoundedHighNarrowLower.Vector64.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddWideningLower.Vector64.Byte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddWideningLower.Vector64.Int16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddWideningLower.Vector64.Int32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddWideningLower.Vector64.SByte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddWideningLower.Vector64.UInt16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AddWideningLower.Vector64.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLower.Vector64.Byte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLower.Vector64.Int16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLower.Vector64.Int32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLower.Vector64.SByte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLower.Vector64.UInt16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLower.Vector64.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndAdd.Vector64.Byte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndAdd.Vector64.Int16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndAdd.Vector64.Int32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndAdd.Vector64.SByte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndAdd.Vector64.UInt16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndAdd.Vector64.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndSubtract.Vector64.Byte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndSubtract.Vector64.Int16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndSubtract.Vector64.Int32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndSubtract.Vector64.SByte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndSubtract.Vector64.UInt16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/MultiplyWideningLowerAndSubtract.Vector64.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningHighNarrowLower.Vector64.Byte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningHighNarrowLower.Vector64.Int16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningHighNarrowLower.Vector64.Int32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningHighNarrowLower.Vector64.SByte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningHighNarrowLower.Vector64.UInt16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningHighNarrowLower.Vector64.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningRoundedHighNarrowLower.Vector64.Byte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningRoundedHighNarrowLower.Vector64.Int16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningRoundedHighNarrowLower.Vector64.Int32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningRoundedHighNarrowLower.Vector64.SByte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningRoundedHighNarrowLower.Vector64.UInt16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractReturningRoundedHighNarrowLower.Vector64.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractWideningLower.Vector64.Byte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractWideningLower.Vector64.Int16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractWideningLower.Vector64.Int32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractWideningLower.Vector64.SByte.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractWideningLower.Vector64.UInt16.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/SubtractWideningLower.Vector64.UInt32.cs		diff \| blob \| history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/GenerateTests.csx		diff \| blob \| history

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