[AArch64]]SME2 multi-vec to multi-vec FP/INT down convert 2/4 registers

[AArch64]]SME2 multi-vec to multi-vec FP/INT down convert 2/4 registers

This patch implements:
 FCVTZS: Multi-vector floating-point convert to signed integer, rounding
         toward zero.
 FCVTZU: Multi-vector floating-point convert to unsigned integer,
        rounding toward zero.
 SCVTF: Multi-vector signed integer convert to floating-point.
 UCVTF: Multi-vector unsigned integer convert to floating-point.
for 2 and 4 registers

The reference can be found here:
    https://developer.arm.com/documentation/ddi0602/2022-09

    Depends on: D135563

Differential Revision: https://reviews.llvm.org/D135593