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(parent: bc3b84d) | patch
ARM: imx: set up pllv3 POWER and BYPASS sequentially
authorShawn Guo <shawn.guo@linaro.org>
Thu, 31 Oct 2013 01:46:17 +0000 (09:46 +0800)
committerShawn Guo <shawn.guo@linaro.org>
Mon, 11 Nov 2013 14:58:45 +0000 (22:58 +0800)
commit43c9b9e8a4c64b1dd3026ab233703a4321ac6d7c
tree214c780126ea7b8507dcb3f1e33d0dc824874386tree | snapshot
parentbc3b84da8a55752d8c54005e558d59ac10fe9953commit | diff
ARM: imx: set up pllv3 POWER and BYPASS sequentially

Currently, POWER and BYPASS bits are set up in a single write to pllv3
register.  This causes problem occasionally from the IPU/HDMI testing.
Let's follow FSL BSP code to set up POWER bit, relock, and then BYPASS
sequentially.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
arch/arm/mach-imx/clk-pllv3.c diff | blob | history
Domain: SCM / Uncategorized;