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(parent: 77507aa) | patch
net/mlx4_core: Cache line EQE size support
authorIdo Shamay <idos@mellanox.com>
Thu, 18 Sep 2014 08:51:00 +0000 (11:51 +0300)
committerDavid S. Miller <davem@davemloft.net>
Fri, 19 Sep 2014 21:30:10 +0000 (17:30 -0400)
commit43c816c67a536cfcfc24da50153115b75eca94f0
tree1079096c4a0b59899c5e953be2b33723776f5c32tree | snapshot
parent77507aa249aecd06fa25ad058b64481e46887a01commit | diff
net/mlx4_core: Cache line EQE size support

Enable mlx4 interrupt handler to work with EQE stride feature,
The feature may be enabled when cache line is bigger than 64B.
The EQE size will then be the cache line size, and the context
segment resides in [0-31] offset.

Signed-off-by: Ido Shamay <idos@mellanox.com>
Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlx4/eq.c diff | blob | history
Domain: System / Kernel;