re PR target/41076 ([avr] pessimal code for logical OR of 8-bit fields)
authorGeorg-Johann Lay <avr@gjlay.de>
Mon, 28 Nov 2016 08:40:11 +0000 (08:40 +0000)
committerGeorg-Johann Lay <gjl@gcc.gnu.org>
Mon, 28 Nov 2016 08:40:11 +0000 (08:40 +0000)
commit43c058162f9ee10a3149b502aa4c76f668b64e34
tree513e93a07159bf6308469a8636ca791b6589140c
parentf9438bbb2e36eea2a61d09ee268704aff4f15d81
re PR target/41076 ([avr] pessimal code for logical OR of 8-bit fields)

PR 41076
* config/avr/avr.md (SPLIT34): New mode iterator.
(bitop): New code iterator.
(*iorhi3.ashift8-*). New insn-and-split patterns.
(*movhi): Post-reload split reg = 0.
[!MOVW]: Post-reload split reg = reg.
(*mov<mode>) [SI,SF,PSI,SQ,USQ,SA,USA]: Post-reload split reg = reg.
(andhi3, andpsi3, andsi3): Post-reload split reg-reg operations.
(iorhi3, iorpsi3, iorsi3): Same.
(xorhi3, xorpsi3, xorsi3): Same.
* config/avr/avr.c (avr_rtx_costs_1) [IOR && HImode]: Adjust rtx
costs to *iorhi3.ashift8-* patterns.

From-SVN: r242907
gcc/ChangeLog
gcc/config/avr/avr.c
gcc/config/avr/avr.md