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(merge: 06c2afb 5c7a71f)
Merge tag 'v6.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind...
authorStephen Boyd <sboyd@kernel.org>
Tue, 22 Aug 2023 17:51:09 +0000 (10:51 -0700)
committerStephen Boyd <sboyd@kernel.org>
Tue, 22 Aug 2023 17:51:09 +0000 (10:51 -0700)
commit438c61a7905abe9053e7f6411cd62b754b5ca4e1
tree9c2c30d878163740e9bbe2ee55a454bb16ba2920tree | snapshot
parent06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5commit | diff
parent5c7a71fd82350c2f5828a66a1f2f38306d61cbc7commit | diff
Merge tag 'v6.6-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - PLL rates for rk3568 and the display clock tree for rv1126 which wasn't present before

* tag 'v6.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rv1126: Add PD_VO clock tree
  clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
  clk: rockchip: rk3568: Add PLL rate for 101MHz
Domain: System / Kernel;