i965: Emit post-sync non-zero flush before 3DSTATE_GS_SVB_INDEX.
authorKenneth Graunke <kenneth@whitecape.org>
Thu, 24 Oct 2013 07:32:52 +0000 (00:32 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Mon, 28 Oct 2013 18:29:27 +0000 (11:29 -0700)
commit436e815a250a8fde22d79093f4b9eed56472693b
treeef9dc661d49f6e3e1fb6ea155d5a7e9dceea7df9
parent32a3f5f6d768e5828be1d1f46b1b3f819f55cba8
i965: Emit post-sync non-zero flush before 3DSTATE_GS_SVB_INDEX.

From the comments above intel_emit_post_sync_nonzero_flush:
"[DevSNB-C+{W/A}] Before any depth stall flush (including those
 produced by non-pipelined state commands), software needs to first
 send a PIPE_CONTROL with no bits set except Post-Sync Operation != 0."

This suggests that every non-pipelined (0x79xx) command needs a
post-sync non-zero flush before it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Xinkai Chen <yeled.nova@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
src/mesa/drivers/dri/i965/gen6_sol.c