RISC-V: Fix pred_mov constraint for vle.v

RISC-V: Fix pred_mov constraint for vle.v

The original constraint is incorrect in pred_mov pattern.
Take a look at Alternative 2, the operands[0] is "vr",
operands[1] which is mask operand can be "vm".
Such alternative matching will give the wrong codegen (vle.v v0,0(a5),v0.t)
This is illegal according to RVV ISA.

To fix this issue and not destroy the RA performance, fix this pattern in
this patch.

gcc/ChangeLog:

	* config/riscv/vector.md: Fix constraints.