RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn, if compiling for Zbb

RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn, if compiling for Zbb

If-conversion is turning '(a >= 0) ? b : 0' into a branchless sequence
	not	a5,a0
	srai	a5,a5,63
	and	a0,a1,a5
missing the opportunity to combine the NOT and AND into an ANDN.

This adds a define_split to help the combiner reassociate the NOT with
the AND.

gcc/ChangeLog:

	* config/riscv/bitmanip.md: New define_split.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbb-srai-andn.c: New test.