RISC-V: Allow instruction require more than one extension
authorJim Wilson <jimw@sifive.com>
Thu, 30 Aug 2018 20:23:12 +0000 (13:23 -0700)
committerJim Wilson <jimw@sifive.com>
Thu, 30 Aug 2018 20:23:12 +0000 (13:23 -0700)
commit43135d3b15ce10a786704f9bb4736d834d6581a8
tree09a46598dd29db01cd479dfc5f23f29abf68f8cb
parenta869991180094d4cbeb0bd2f275fc7b30e513fb7
RISC-V: Allow instruction require more than one extension

2018-08-29  Kito Cheng  <kito@andestech.com>

gas/
* config/tc-riscv.c (riscv_subset_supports): New argument:
xlen_required.
(riscv_multi_subset_supports): New function, able to check more
than one extension.
(riscv_ip): Use riscv_multi_subset_supports instead of
riscv_subset_supports.
(riscv_set_arch): Update call-site for riscv_subset_supports.
(riscv_after_parse_args): Likewise.

include/
*opcode/riscv.h (MAX_SUBSET_NUM): New.
(riscv_opcode): Add xlen_requirement field and change type of
subset.

opcodes/
* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
riscv_opcode.xlen_requirement.
* riscv-opc.c (riscv_opcodes): Update for struct change.
gas/ChangeLog
gas/config/tc-riscv.c
include/ChangeLog
include/opcode/riscv.h
opcodes/ChangeLog
opcodes/riscv-dis.c
opcodes/riscv-opc.c