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armv8: fsl-layerscape: Add back L3 flushing for all exception levels
authorYork Sun <york.sun@nxp.com>
Fri, 8 Sep 2017 16:33:49 +0000 (09:33 -0700)
committerYork Sun <york.sun@nxp.com>
Mon, 11 Sep 2017 15:02:13 +0000 (08:02 -0700)
commit42f43aa25876d1c77002ee5f333ab36dcb01d719
tree5841dcef0e5745e02dd16b8f9c9fe89c541e2d92tree | snapshot
parent4950eb4a48623d8ad013c1f37097906ec52040d1commit | diff
armv8: fsl-layerscape: Add back L3 flushing for all exception levels

CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.

Signed-off-by: York Sun <york.sun@nxp.com>
Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S diff | blob | history
Domain: System / Kernel;