drm/i915: IVB/HSW have 32 fence register
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 9 Apr 2013 10:02:47 +0000 (13:02 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 18 Apr 2013 07:43:21 +0000 (09:43 +0200)
commit42b5aeabe9286cdaabfc9b0ce5fa869bbe04dcd9
treee4b999560b685a301ca250853fce17dd285e62e4
parent182642b09311c94898acbc01cc9bac8e02f63da6
drm/i915: IVB/HSW have 32 fence register

Increase the number of fence registers to 32 on IVB/HSW. VLV however
only has 16 fence registers according to the docs.

Increasing the number of fences was attempted before [1], but there was
some uncertainty about the maximum CPU fence number for FBC. Since then
BSpec has been updated to state that there are in fact 32 fence registers,
and the CPU fence number field in the SNB_DPFC_CTL_SA register is 5 bits,
and the CPU fence number field in the ILK_DPFC_CONTROL register must be
zero. So now it all makes sense.

[1] http://lists.freedesktop.org/archives/intel-gfx/2011-October/012865.html

v2: Include some background information based on the previous attempt

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_irq.c