intel/fs: make tcs input_vertices dynamic
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Sat, 8 Apr 2023 18:34:35 +0000 (21:34 +0300)
committerMarge Bot <emma+marge@anholt.net>
Wed, 24 May 2023 18:32:07 +0000 (18:32 +0000)
commit429ef02f83e6516ec984caefba5046c939c6b8ee
tree113e2cc4e9fe610c97d6051fdfde85bc28380227
parent32b7659fffb4d023d6564e1af44a8e9b94981870
intel/fs: make tcs input_vertices dynamic

We need to do 3 things to accomplish this :

   1. make all the register access consider the maximal case when
      unknown at compile time

   2. move the clamping of load_per_vertex_input prior to lowering
      nir_intrinsic_load_patch_vertices_in (in the dynamic cases, the
      clamping will use the nir_intrinsic_load_patch_vertices_in to
      clamp), meaning clamping using derefs rather than lowered
      nir_intrinsic_load_per_vertex_input

   3. in the known cases, lower nir_intrinsic_load_patch_vertices_in
      in NIR (so that the clamped elements still be vectorized to the
      smallest number of URB read messages)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22378>
src/intel/compiler/brw_compiler.h
src/intel/compiler/brw_fs_nir.cpp
src/intel/compiler/brw_fs_thread_payload.cpp
src/intel/compiler/brw_nir.c
src/intel/compiler/brw_nir.h
src/intel/compiler/brw_nir_clamp_per_vertex_loads.c
src/intel/compiler/brw_vec4_tcs.cpp