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(parent: cb6c386) | patch
[X86] Make FeatureAVX512 imply FeatureF16C.
authorCraig Topper <craig.topper@intel.com>
Mon, 6 Nov 2017 22:49:04 +0000 (22:49 +0000)
committerCraig Topper <craig.topper@intel.com>
Mon, 6 Nov 2017 22:49:04 +0000 (22:49 +0000)
commit428a4e6374e34dd1a810823e6a59bd5ea6cafd0a
tree51454e176a2590b96035b84c6091b6eee30ab0betree | snapshot
parentcb6c38612e7b46d92820a5e000ddc9532086b20fcommit | diff
[X86] Make FeatureAVX512 imply FeatureF16C.

The EVEX to VEX pass is already assuming this is true under AVX512VL. We had special patterns to use zmm instructions if VLX and F16C weren't available.

Instead just make AVX512 imply F16C to make the EVEX to VEX behavior explicitly legal and remove the extra patterns.

All known CPUs with AVX512 have F16C so this should safe for now.

llvm-svn: 317521
llvm/lib/Target/X86/X86.td diff | blob | history
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/lib/Target/X86/X86InstrAVX512.td diff | blob | history
llvm/lib/Target/X86/X86InstrInfo.td diff | blob | history
llvm/test/CodeGen/X86/vec_fp_to_int.ll diff | blob | history
llvm/test/CodeGen/X86/vector-half-conversions.ll diff | blob | history
Domain: System / Toolchain;