drm/i915: Allow the user to set bo into the DISPLAY cache domain
authorChris Wilson <chris@chris-wilson.co.uk>
Thu, 8 Aug 2013 13:41:11 +0000 (14:41 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 22 Aug 2013 11:31:39 +0000 (13:31 +0200)
commit4257d3ba3b87a84adb2f840620cb63512f0bab22
treeb815c7608223763185e57f2d628ca6a5590e48f5
parent651d794fae9b79237aae1c97f8a9d9f3817bd31d
drm/i915: Allow the user to set bo into the DISPLAY cache domain

This is primarily for the benefit of the create2 ioctl so that the
caller can avoid the later step of rebinding the bo with new PTE bits.
After introducing WT (and possibly GFDT) cacheing for display targets,
not everything in the display is earmarked as UC, and more importantly
what is is controlled by the kernel.

Note that set_cache_level/get_cache_level for DISPLAY is not necessarily
idempotent; get_cache_level may return UC for architectures that have no
special cache domain for the display engine.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem.c