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(parent: ea09a42) | patch
[DAG] Fold (sra (or (shl x, c1), (shl y, c2)), c1) -> (sext_inreg (or x, (shl y,c2...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 19 Oct 2022 10:18:39 +0000 (11:18 +0100)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 19 Oct 2022 10:18:49 +0000 (11:18 +0100)
commit42230efccf8fe1185be5fa6c23dce0a8183d6ec9
treebb4f60ee3dbe48c88ef504ea33ae37560616cbc1tree | snapshot
parentea09a426a94cdd1cdf96cf0d22f16f566aee3916commit | diff
[DAG] Fold (sra (or (shl x, c1), (shl y, c2)), c1) -> (sext_inreg (or x, (shl y,c2-c1)) iff c2 >= c1

Helps with some of the AMDGPU regressions identified in D136042 where we were losing signed BFE patterns after sinking shifts behind logic ops.

Differential Revision: https://reviews.llvm.org/D136081
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/bfe-patterns.ll diff | blob | history
Domain: System / Toolchain;