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[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32...
authorCraig Topper <craig.topper@sifive.com>
Fri, 11 Jun 2021 00:05:34 +0000 (17:05 -0700)
committerCraig Topper <craig.topper@sifive.com>
Fri, 11 Jun 2021 02:06:45 +0000 (19:06 -0700)
commit420bd5ee8ec996a2c2e305541e59465a5ba436e3
tree8d07d596c2618f9cff2f97661f8048c9527f3890tree | snapshot
parent7836d058c7e115eace62e324ef6c01670326f518commit | diff
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.

This helps us select W instructions in more cases. Most of the
affected tests have had the sign_extend_inreg or AND folded into
sextload/zextload.

Differential Revision: https://reviews.llvm.org/D104079
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoB.td diff | blob | history
llvm/test/CodeGen/RISCV/double-convert.ll diff | blob | history
llvm/test/CodeGen/RISCV/float-convert.ll diff | blob | history
llvm/test/CodeGen/RISCV/half-convert.ll diff | blob | history
llvm/test/CodeGen/RISCV/rem.ll diff | blob | history
llvm/test/CodeGen/RISCV/rv64zbb.ll diff | blob | history
Domain: System / Toolchain;