RISC-V: Align SBI probe implementation with spec
authorAndrew Jones <ajones@ventanamicro.com>
Thu, 27 Apr 2023 16:36:26 +0000 (18:36 +0200)
committerPalmer Dabbelt <palmer@rivosinc.com>
Sat, 29 Apr 2023 20:04:50 +0000 (13:04 -0700)
commit41cad8284d5e6bf1d49d3c10a6b52ee1ae866a20
tree5ec9f85ff9226487c9e5bafa47a4a69338ca8915
parente4ef93edd4e0b022529303db1915766ff9de450e
RISC-V: Align SBI probe implementation with spec

sbi_probe_extension() is specified with "Returns 0 if the given SBI
extension ID (EID) is not available, or 1 if it is available unless
defined as any other non-zero value by the implementation."
Additionally, sbiret.value is a long. Fix the implementation to
ensure any nonzero long value is considered a success, rather
than only positive int values.

Fixes: b9dcd9e41587 ("RISC-V: Add basic support for SBI v0.2")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20230427163626.101042-1-ajones@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/sbi.h
arch/riscv/kernel/cpu_ops.c
arch/riscv/kernel/sbi.c
arch/riscv/kvm/main.c
drivers/cpuidle/cpuidle-riscv-sbi.c
drivers/perf/riscv_pmu_sbi.c