projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: f93b42a) | patch
[PowerPC] Support constrained vector fp/int conversion
authorQiu Chaofan <qiucofan@cn.ibm.com>
Mon, 24 Aug 2020 02:10:27 +0000 (10:10 +0800)
committerQiu Chaofan <qiucofan@cn.ibm.com>
Mon, 24 Aug 2020 02:10:27 +0000 (10:10 +0800)
commit41ba9d77231eac32f8a022eedffd261c47020dd4
treeaa9b122befe074333cc38115aafe99cf1c02bf7dtree | snapshot
parentf93b42a629ae5865bf71f8062553125b8684deafcommit | diff
[PowerPC] Support constrained vector fp/int conversion

This patch makes these operations legal, and add necessary codegen
patterns.

There's still some issue similar to D77033 for conversion from v1i128
type. But normal type tests synced in vector-constrained-fp-intrinsic
are passed successfully.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D83654
llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCISelLowering.h diff | blob | history
llvm/lib/Target/PowerPC/PPCInstrVSX.td diff | blob | history
llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll diff | blob | history
Domain: System / Toolchain;