clk: renesas: Add r8a7742 CPG Core Clock Definitions
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thu, 23 Apr 2020 21:40:47 +0000 (22:40 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 28 Apr 2020 07:54:25 +0000 (09:54 +0200)
commit41b2df22fafbca2c69dcce9f93c7042e6ccd69ef
tree4b0a1c64bbfe9a2b260669df5c7bce943be0cf40
parent58f7381c97547db025970423bd2a3b9d9cea1174
clk: renesas: Add r8a7742 CPG Core Clock Definitions

Add all RZ/G1H Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2a ("List of Clocks [RZ/G1H]") of the RZ/G1 Hardware User's
Manual.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1587678050-23468-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
include/dt-bindings/clock/r8a7742-cpg-mssr.h [new file with mode: 0644]