[X86] lowerShuffleAsVTRUNC - support offseted truncations
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 13 Dec 2022 13:42:16 +0000 (13:42 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 13 Dec 2022 14:00:35 +0000 (14:00 +0000)
commit4177e6cd4f96903b57dc166118149a3ff8e65c4d
treed6a7ba7c7cb3a6c0a6a0c42cd50b4ad771161567
parent7602e09b1c530bf60028b8c5e508139e6db6e91a
[X86] lowerShuffleAsVTRUNC - support offseted truncations

Extend the <0,Scale,2*Scale,..> pattern to allow for a fixed offset <Offset,Offset+Scale,Offset+2*Scale,..> pattern, which will lower to a single additional bitshift/pshufd.

At the moment I've limited this to cases where the LHS/RHS operands are concatenated for free, but this is only to avoid a couple of regressions that should be easily addressable in followups.
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
llvm/test/CodeGen/X86/x86-interleaved-access.ll