[AArch64] Add sign bits handling for vector compare nodes
authorDavid Green <david.green@arm.com>
Tue, 2 May 2023 10:05:35 +0000 (11:05 +0100)
committerDavid Green <david.green@arm.com>
Tue, 2 May 2023 10:05:35 +0000 (11:05 +0100)
commit41549b535097db923386a64ed769bf450943e6a3
treecc3dd40d832bb095fbecaee15c3157ad7acc7e3a
parentda942fee5bb80c2fb81fbb914304e94103cc25a5
[AArch64] Add sign bits handling for vector compare nodes

This adds ComputeNumSignBits for the NEON vector comparison nodes, which all
either return 0 or -1. Also adds sign_extend_inreg from VASHR+VSHL to show it
performing transforms.

Differential Revision: https://reviews.llvm.org/D148624
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/test/CodeGen/AArch64/cmp-select-sign.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll