projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ddaa4b4) | patch
[ARM] Allowing SP/PC for AND/BIC mod_imm_not
authorRenato Golin <renato.golin@linaro.org>
Tue, 8 Dec 2015 18:10:58 +0000 (18:10 +0000)
committerRenato Golin <renato.golin@linaro.org>
Tue, 8 Dec 2015 18:10:58 +0000 (18:10 +0000)
commit412ee3d45dc54b44e603ed5851f2f0f976c1e19f
tree7094bfff35dd0013894b326ccccb989000b3f68atree | snapshot
parentddaa4b4990ba32282dc2c91b7251aff50f9f3dc6commit | diff
[ARM] Allowing SP/PC for AND/BIC mod_imm_not

AND/BIC instructions do accept SP/PC, so the register class should be
more generic (rGPR -> GPR) to cope with that case. Adding more tests.

llvm-svn: 255034
llvm/lib/Target/ARM/ARMInstrInfo.td diff | blob | history
llvm/test/MC/ARM/basic-arm-instructions.s diff | blob | history
Domain: System / Toolchain;