[RISCV] Add a special case to treat riscv-v-vector-bits-min=-1 as meaning use Zvl...
authorCraig Topper <craig.topper@sifive.com>
Wed, 4 May 2022 21:26:44 +0000 (14:26 -0700)
committerCraig Topper <craig.topper@sifive.com>
Wed, 4 May 2022 21:26:45 +0000 (14:26 -0700)
commit411bb42eed723ba8e8ae29a59cbc7aacc6bab774
tree1680075723c51ff339cb8cffbfd798333dbb66ee
parent5e004fb787698440a387750db7f8028e7cb14cfc
[RISCV] Add a special case to treat riscv-v-vector-bits-min=-1 as meaning use Zvl*b value.

riscv-v-vector-bits-min is primarily used to opt-in to the
autovectorizer. The vector width can be determined from Zvl*b.

This patch adds support treating -1 as meaning use Zvl*b so we can
still opt-in to autovectorization without needing to repeat a
vector width already given by Zvl*b or -mcpu.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D124960
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll