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(parent: a29d4b3) | patch
drm/amdgpu: fix CGTS_TCC_DISABLE register offset on gfx10.3
authorMarek Olšák <marek.olsak@amd.com>
Thu, 4 Feb 2021 07:46:20 +0000 (02:46 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 18 Feb 2021 21:42:55 +0000 (16:42 -0500)
commit4112c00354004cbb1bf56f0114fa9951bf6b13ed
tree4600616629e5826306e63ecacfebc3dbf998cdf4tree | snapshot
parenta29d4b3d3caf91beba12187e4c78ec28e4a29c09commit | diff
drm/amdgpu: fix CGTS_TCC_DISABLE register offset on gfx10.3

This fixes incorrect TCC harvesting info reported to userspace.
The impact was a very very tiny performance degradation (unnecessary
GL2 cache flushes).

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c diff | blob | history
Domain: System / Kernel;