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[DAGCombiner] Teach createBuildVecShuffle to handle cases where input vectors are...
authorCraig Topper <craig.topper@gmail.com>
Fri, 14 Oct 2016 06:00:42 +0000 (06:00 +0000)
committerCraig Topper <craig.topper@gmail.com>
Fri, 14 Oct 2016 06:00:42 +0000 (06:00 +0000)
commit40feb7f1570ab6f0d05993dc1513a9760a905c4c
treea68aaeabed153bc543d306ecae71a7a306eaf108tree | snapshot
parent2bd52b5d91f7f560f86eb60a7852e5c2f44aefa3commit | diff
[DAGCombiner] Teach createBuildVecShuffle to handle cases where input vectors are less than half of the output vector size.

This will be needed by a future commit to support sign/zero extending from v8i8 to v8i64 which requires a sign/zero_extend_vector_inreg to be created which requires v8i8 to be concatenated upto v64i8 and goes through this code.

llvm-svn: 284204
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
llvm/test/CodeGen/X86/avx512-build-vector.ll diff | blob | history
llvm/test/CodeGen/X86/vec_extract-avx.ll diff | blob | history
Domain: System / Toolchain;