RISC-V: Fix regression of -fzero-call-used-regs=all [PR109104]
authorYanzhang Wang <yanzhang.wang@intel.com>
Tue, 11 Apr 2023 11:37:48 +0000 (19:37 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Tue, 11 Apr 2023 14:02:41 +0000 (22:02 +0800)
commit40fc8e3d4f600d89e6b065d6f12db7a816269c8f
tree0159b34bd41711e3c0d27754bbe279288b7a2cd2
parentb8e32978e3d9e3b88cd4f441edfdebfa395a5c26
RISC-V: Fix regression of -fzero-call-used-regs=all [PR109104]

This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.

gcc/ChangeLog:

PR target/109104
* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl): New.
* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl): New.
(emit_vlmax_vsetvl): Use emit_hard_vlmax_vsetvl.
* config/riscv/riscv.cc (vector_zero_call_used_regs): New.
(riscv_zero_call_used_regs): New.
(TARGET_ZERO_CALL_USED_REGS): New.

gcc/testsuite/ChangeLog:

PR target/109104
* gcc.target/riscv/zero-scratch-regs-1.c: New test.
* gcc.target/riscv/zero-scratch-regs-2.c: New test.
* gcc.target/riscv/zero-scratch-regs-3.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
gcc/config/riscv/riscv-protos.h
gcc/config/riscv/riscv-v.cc
gcc/config/riscv/riscv.cc
gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c [new file with mode: 0644]