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[RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XOR/MIN/MAX/CLMUL
authorCraig Topper <craig.topper@sifive.com>
Mon, 25 Apr 2022 17:45:48 +0000 (10:45 -0700)
committerCraig Topper <craig.topper@sifive.com>
Mon, 25 Apr 2022 17:53:41 +0000 (10:53 -0700)
commit40f1af47601044149102b1597d5f56689661f8a5
tree63358a35011a559c894d08832a0ab6b9d9d5d8dbtree | snapshot
parent1159984802e736dc85395ffa589bb65c1005b95acommit | diff
[RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XOR/MIN/MAX/CLMUL

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D123970
llvm/lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoM.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td diff | blob | history
llvm/test/CodeGen/RISCV/machine-cse.ll [new file with mode: 0644] blob
Domain: System / Toolchain;