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(parent: 0903ea6) | patch
clk: sunxi: register factors clocks behind composite
authorEmilio López <emilio@elopez.com.ar>
Mon, 23 Dec 2013 03:32:32 +0000 (00:32 -0300)
committerEmilio López <emilio@elopez.com.ar>
Sat, 28 Dec 2013 20:07:42 +0000 (17:07 -0300)
commit40a5dcba4e79023f0b511dc0ca498bdf9eacb5db
treecb8669f36dde36c379ae806f3c54e2e1c0d87efbtree | snapshot
parent0903ea60173fab226a867ceb080b2e0269a6c975commit | diff
clk: sunxi: register factors clocks behind composite

This commit reworks factors clock registration to be done behind a
composite clock. This allows us to additionally add a gate, mux or
divisors, as it will be needed by some future PLLs.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/sunxi/clk-factors.c diff | blob | history
drivers/clk/sunxi/clk-factors.h diff | blob | history
drivers/clk/sunxi/clk-sunxi.c diff | blob | history
Domain: System / Kernel;