[RISCV] Add RV32 test cases for vsoxseg.
authorHsiangkai Wang <kai.wang@sifive.com>
Thu, 21 Jan 2021 15:40:15 +0000 (23:40 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Sat, 23 Jan 2021 00:54:56 +0000 (08:54 +0800)
commit408ed11c85d9e70131b77a9125775ace3643663c
treed1daa72eefeb6f627d976596bcdafd6a23bd71ab
parent438e118c29a0610dbd44569aff54b5d87684b333
[RISCV] Add RV32 test cases for vsoxseg.

Differential Revision: https://reviews.llvm.org/D95194
llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll [new file with mode: 0644]