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(parent: dc2b9c7) | patch
drm/amdgpu: Write masked value to control register
authorMaíra Canal <mairacanal@riseup.net>
Thu, 14 Jul 2022 16:44:56 +0000 (13:44 -0300)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 20 Jul 2022 20:03:59 +0000 (16:03 -0400)
commit40835624efcde7f984cb859035b95b5a526d1a9f
tree79f64a11d012c2b461e3492a9a1bde4ab66e1ef9tree | snapshot
parentdc2b9c70ebca8e5661d33a15ed2b99d4510e90becommit | diff
drm/amdgpu: Write masked value to control register

On the dce_v6_0 and dce_v8_0 hpd tear down callback, the tmp variable
should be written into the control register instead of 0.

Reviewed-by: André Almeida <andrealmeid@igalia.com>
Signed-off-by: Maíra Canal <mairacanal@riseup.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c diff | blob | history
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c diff | blob | history
Domain: System / Kernel;