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author	Craig Topper <craig.topper@sifive.com>
	Fri, 17 Mar 2023 02:34:16 +0000 (19:34 -0700)
committer	Craig Topper <craig.topper@sifive.com>
	Fri, 17 Mar 2023 02:42:33 +0000 (19:42 -0700)
commit	4063369fd452b9bb9941494023eea6395a1872d3
tree	bc684c20a54affdbcb893f19caca350f328c17ed	tree \| snapshot
parent	35c05f04e547100d03b6359d1f66950ff83350e0	commit \| diff

[RISCV] Add MULW to RISCVStripWSuffix.

This converts MULW to MUL if the upper bits aren't used.
This will give more opportunities to use c.mul with Zcb.

21 files changed:

llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp		diff \| blob \| history
llvm/test/CodeGen/RISCV/addimm-mulimm.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/bitextract-mac.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/machine-combiner.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/machine-outliner-throw.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/sadd_sat_plus.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/sextw-removal.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/srem-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/srem-vector-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/ssub_sat_plus.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/uadd_sat_plus.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/urem-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/urem-vector-lkk.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/usub_sat_plus.ll		diff \| blob \| history

Domain: System / Toolchain;

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