arm: socfpga: Changed to store QSPI reference clock in kHz
authorSiew Chin Lim <elly.siew.chin.lim@intel.com>
Wed, 24 Mar 2021 09:16:50 +0000 (17:16 +0800)
committerLey Foon Tan <ley.foon.tan@intel.com>
Thu, 8 Apr 2021 09:29:12 +0000 (17:29 +0800)
commit404a98b0a49853e02ea342f6873b38702dd122c7
treef225593602fe17de7fce1e520b8f8ddb5bb57c96
parent3aef59f28083e2e3bd0c7ad91230f573123ec848
arm: socfpga: Changed to store QSPI reference clock in kHz

Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.

This patch is in preparation for Intel N5X SDRAM driver
support. Reserved 4 bits for Intel N5X SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to limited bits, QSPI reference clock frequency is
converted to kHz from Hz.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
arch/arm/mach-socfpga/clock_manager.c
arch/arm/mach-socfpga/include/mach/clock_manager.h
arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
arch/arm/mach-socfpga/mailbox_s10.c