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(parent: f01d7d5) | patch
perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints
authorKan Liang <kan.liang@linux.intel.com>
Thu, 26 Aug 2021 15:32:43 +0000 (08:32 -0700)
committerPeter Zijlstra <peterz@infradead.org>
Tue, 31 Aug 2021 11:59:37 +0000 (13:59 +0200)
commit4034fb207e302cc0b1f304084d379640c1fb1436
tree5cdc7438263a5e1ccd1a7945414421999a12f8bbtree | snapshot
parentf01d7d558e1855d4aa8e927b86111846536dd476commit | diff
perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints

SPR M3UPI have the exact same event constraints as ICX, so add the
constraints.

Fixes: 2a8e51eae7c8 ("perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-8-git-send-email-kan.liang@linux.intel.com
arch/x86/events/intel/uncore_snbep.c diff | blob | history
Domain: System / Kernel;