dt-bindings: clk: document PolarFire SoC fabric clocks
authorConor Dooley <conor.dooley@microchip.com>
Thu, 8 Sep 2022 14:36:49 +0000 (15:36 +0100)
committerClaudiu Beznea <claudiu.beznea@microchip.com>
Wed, 14 Sep 2022 07:57:07 +0000 (10:57 +0300)
commit3ffb5ad24d0064f923ed30ad37e33e56eee31f2b
tree44bce7694fabd3e3a0ac83fa38e5a6a5f19d3e4f
parent803307a452e787af92789db16a156c35e60f8aaf
dt-bindings: clk: document PolarFire SoC fabric clocks

On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the
ordinal corners of the chip, which our documentation refers to as
"Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are
highly configurable & many of the input clocks are optional.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-3-conor.dooley@microchip.com
Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml [new file with mode: 0644]