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(parent: 899f809) | patch
clk: tegra: Correct parent of the APBDMA clock
authorDmitry Osipenko <digetx@gmail.com>
Tue, 3 Oct 2017 23:02:39 +0000 (02:02 +0300)
committerThierry Reding <treding@nvidia.com>
Wed, 1 Nov 2017 14:00:04 +0000 (15:00 +0100)
commit3ff46fd0b22abbb8d921d7e5657912bfbd41b6f0
treee2a7e4414151d8d37502ab06abbc5d28cabf482ftree | snapshot
parent899f8095e66c562888ff617686e46019b758611bcommit | diff
clk: tegra: Correct parent of the APBDMA clock

APBDMA represents a clock gate to the APB DMA controller, the actual
clock source for the controller is PCLK.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra-periph.c diff | blob | history
Domain: System / Kernel;