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[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits
authorAlex Bradbury <asb@lowrisc.org>
Wed, 18 Apr 2018 20:34:23 +0000 (20:34 +0000)
committerAlex Bradbury <asb@lowrisc.org>
Wed, 18 Apr 2018 20:34:23 +0000 (20:34 +0000)
commit3ff2022bb940237f10584d81da8d21bd62e76c7d
tree41284359b11859abf59ef75e2a3b238a7da3362btree | snapshot
parentf4a3ff008d58fca4031f03644d96a634cd9815bacommit | diff
[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits

These immediates can be materialised with just an lui, rather than an lui+addi
pair.

llvm-svn: 330293
llvm/lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll diff | blob | history
llvm/test/CodeGen/RISCV/calling-conv.ll diff | blob | history
llvm/test/CodeGen/RISCV/float-arith.ll diff | blob | history
llvm/test/CodeGen/RISCV/imm.ll diff | blob | history
llvm/test/CodeGen/RISCV/vararg.ll diff | blob | history
Domain: System / Toolchain;