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(parent: 04cd0a0) | patch
ata: ahci: Add BAR index quirk for Cavium PCI SATA device
authorSuneel Garapati <sgarapati@marvell.com>
Sun, 20 Oct 2019 00:48:25 +0000 (17:48 -0700)
committerStefan Roese <sr@denx.de>
Tue, 25 Aug 2020 06:01:16 +0000 (08:01 +0200)
commit3f6f0cd8fd809287838153d355311f1499040758
tree4d4dd7e78d49b8bd1d32132f651893fb6e138302tree | snapshot
parent04cd0a0fa03968405918fa6f6b695821767fb068commit | diff
ata: ahci: Add BAR index quirk for Cavium PCI SATA device

For SATA controller found on OcteonTX SoC's, use non-standard PCI BAR0
instead of BAR5.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
drivers/ata/ahci.c diff | blob | history
Domain: System / Kernel;