drm/i915: Match all PSR mode entry conditions before enabling it.
authorRodrigo Vivi <rodrigo.vivi@gmail.com>
Thu, 11 Jul 2013 21:45:00 +0000 (18:45 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 18 Jul 2013 08:17:21 +0000 (10:17 +0200)
commit3f51e4713fc57ab0fc225c3f0e67578a53c24a11
tree805ccec916c12cc168dfb34a8bd07d957d69e654
parente91fd8c6dec2ffa903b4f695fce4b9d7248ed2d5
drm/i915: Match all PSR mode entry conditions before enabling it.

v2: Prefer seq_puts to seq_printf by Paulo Zanoni.
v3: small changes like avoiding calling dp_to_dig_port twice as noticed by
    Paulo Zanoni.
v4: Avoiding reading non-existent registers - noticed by Paulo
    on first psr debugfs patch.
v5: Accepting more suggestions from Paulo:
    * check sw interlace flag instead of i915_read
    * introduce PSR_S3D_ENABLED to avoid forgeting it whenever added.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
[danvet: Fix up debugfs output (spotted by Paulo) and rip out the
power well check since we really can't do that in a race-free manner,
so it's bogus.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_dp.c