drm/i915/icl: DSI vswing programming sequence
authorMadhav Chauhan <madhav.chauhan@intel.com>
Sun, 16 Sep 2018 10:53:25 +0000 (16:23 +0530)
committerJani Nikula <jani.nikula@intel.com>
Mon, 24 Sep 2018 14:17:49 +0000 (17:17 +0300)
commit3f4b9d9d02c6239f5d0eae6f59af5252ef8beefd
tree4104592c5267cd35d931e47462afa5847a5a22f3
parentfc41001d97083fba638b9bbbf84c72db735c1680
drm/i915/icl: DSI vswing programming sequence

This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.

v2: Rebase
v3: Address various review comments related to VSWING
    programming (Jani N)

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1537095223-5184-3-git-send-email-madhav.chauhan@intel.com
drivers/gpu/drm/i915/icl_dsi.c