riscv: dts: fix the mpfs's reference clock frequency
authorConor Dooley <conor.dooley@microchip.com>
Tue, 25 Oct 2022 07:58:49 +0000 (08:58 +0100)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Tue, 15 Nov 2022 07:37:17 +0000 (15:37 +0800)
commit3f3527044d7460543b69931c3385925119dcf945
tree6d46a16cc5a82bfbf729a4f6ab92593192413494
parent4e405c68fbf53e52fdb36631caa090c081c59bd0
riscv: dts: fix the mpfs's reference clock frequency

The initial devicetree for PolarFire SoC incorrectly created a fixed
frequency clock in the devicetree to represent the msspll, but the
msspll is not a fixed frequency clock. The actual reference clock on a
board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit.
Swap the incorrect representation of the msspll out for the actual
reference clock.

Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
arch/riscv/dts/microchip-mpfs-icicle-kit.dts
arch/riscv/dts/microchip-mpfs.dtsi