For 128/256-bit vec_cond_expr, When mask operands is lt reg const0_rtx, blendv can...
authorliuhongt <hongtao.liu@intel.com>
Mon, 24 May 2021 02:57:52 +0000 (10:57 +0800)
committerliuhongt <hongtao.liu@intel.com>
Mon, 28 Jun 2021 01:17:36 +0000 (09:17 +0800)
commit3f1a08d9d731975d4061c306837ab28d52f37c7e
tree68001ffd1da3a0ded053ace7d5fa4280d902ce92
parent28560c6d4043d8f6ac570f35fb84e952e9c719fe
For 128/256-bit vec_cond_expr, When mask operands is lt reg const0_rtx, blendv can be used instead of avx512 mask.

gcc/ChangeLog:

PR target/100648
* config/i386/sse.md (*avx_cmp<mode>3_lt): New
define_insn_and_split.
(*avx_cmp<mode>3_ltint): Ditto.
(*avx2_pcmp<mode>3_3): Ditto.
(*avx2_pcmp<mode>3_4): Ditto.
(*avx2_pcmp<mode>3_5): Ditto.

gcc/testsuite/ChangeLog:

PR target/100648
* g++.target/i386/avx2-pr54700-2.C: Adjust testcase.
* g++.target/i386/avx512vl-pr54700-1a.C: New test.
* g++.target/i386/avx512vl-pr54700-1b.C: New test.
* g++.target/i386/avx512vl-pr54700-2a.C: New test.
* g++.target/i386/avx512vl-pr54700-2b.C: New test.
* gcc.target/i386/avx512vl-pr100648.c: New test.
* gcc.target/i386/avx512vl-blendv-1.c: New test.
* gcc.target/i386/avx512vl-blendv-2.c: New test.
gcc/config/i386/sse.md
gcc/testsuite/g++.target/i386/avx2-pr54700-2.C
gcc/testsuite/g++.target/i386/avx512vl-pr54700-1a.C [new file with mode: 0644]
gcc/testsuite/g++.target/i386/avx512vl-pr54700-1b.C [new file with mode: 0644]
gcc/testsuite/g++.target/i386/avx512vl-pr54700-2a.C [new file with mode: 0644]
gcc/testsuite/g++.target/i386/avx512vl-pr54700-2b.C [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/avx512vl-blendv-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/avx512vl-blendv-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/avx512vl-pr100648.c [new file with mode: 0644]