intel/fs: Represent SWSB in-order dependency addresses as vectors.

intel/fs: Represent SWSB in-order dependency addresses as vectors.

This extends the current ordered_address instruction counter to a
vector with one component per asynchronous ALU pipeline, allowing us
to track the last instruction that accessed a register separately for
each ALU pipeline of the XeHP EU, making it straightforward to
infer the right cross-pipeline synchronization annotations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
v2: Make unit tests happy (with ubsan as run by GitLab automation).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>