[ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic plus operator.
authorSrinath Parvathaneni <srinath.parvathaneni@arm.com>
Fri, 20 Mar 2020 11:44:08 +0000 (11:44 +0000)
committerKyrylo Tkachov <kyrylo.tkachov@arm.com>
Fri, 20 Mar 2020 11:44:08 +0000 (11:44 +0000)
commit3eff57aacfef6e05f55e9dd6ecae3ef8568aaac4
treed54a666157f3d98c375e0ad11f67cc0b527bb746
parent7d4549b2cd209eb621453ce13be7ffd84ffa720a
[ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic plus operator.

This patch supports following MVE ACLE vaddq intrinsics. The RTL patterns for this intrinsics are added using arithmetic "plus" operator.

vaddq_s8, vaddq_s16, vaddq_s32, vaddq_u8, vaddq_u16, vaddq_u32, vaddq_f16, vaddq_f32.

Please refer to M-profile Vector Extension (MVE) intrinsics [1]  for more details.
[1]  https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics

2020-03-20  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
            Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>

* config/arm/arm_mve.h (vaddq_s8): Define macro.
(vaddq_s16): Likewise.
(vaddq_s32): Likewise.
(vaddq_u8): Likewise.
(vaddq_u16): Likewise.
(vaddq_u32): Likewise.
(vaddq_f16): Likewise.
(vaddq_f32): Likewise.
(__arm_vaddq_s8): Define intrinsic.
(__arm_vaddq_s16): Likewise.
(__arm_vaddq_s32): Likewise.
(__arm_vaddq_u8): Likewise.
(__arm_vaddq_u16): Likewise.
(__arm_vaddq_u32): Likewise.
(__arm_vaddq_f16): Likewise.
(__arm_vaddq_f32): Likewise.
(vaddq): Define polymorphic variant.
* config/arm/iterators.md (VNIM): Define mode iterator for common types
Neon, IWMMXT and MVE.
(VNINOTM): Likewise.
* config/arm/mve.md (mve_vaddq<mode>): Define RTL pattern.
(mve_vaddq_f<mode>): Define RTL pattern.
* config/arm/neon.md (add<mode>3): Rename to addv4hf3 RTL pattern.
(addv8hf3_neon): Define RTL pattern.
* config/arm/vec-common.md (add<mode>3): Modify standard add RTL pattern
to support MVE.
(addv8hf3): Define standard RTL pattern for MVE and Neon.
(add<mode>3): Modify existing standard add RTL pattern for Neon and IWMMXT.

gcc/testsuite/ChangeLog:

2020-03-20  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
            Andre Vieira  <andre.simoesdiasvieira@arm.com>
            Mihail Ionescu  <mihail.ionescu@arm.com>

* gcc.target/arm/mve/intrinsics/vaddq_f16.c: New test.
* gcc.target/arm/mve/intrinsics/vaddq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_u8.c: Likewise.
15 files changed:
gcc/ChangeLog
gcc/config/arm/arm_mve.h
gcc/config/arm/iterators.md
gcc/config/arm/mve.md
gcc/config/arm/neon.md
gcc/config/arm/vec-common.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c [new file with mode: 0644]
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c [new file with mode: 0644]
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c [new file with mode: 0644]
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c [new file with mode: 0644]
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c [new file with mode: 0644]
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c [new file with mode: 0644]
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c [new file with mode: 0644]
gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c [new file with mode: 0644]