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(parent: 078a3eb) | patch
clk: at91: rework PLL rate calculation
authorBoris BREZILLON <boris.brezillon@free-electrons.com>
Tue, 2 Sep 2014 07:50:15 +0000 (09:50 +0200)
committerMike Turquette <mturquette@linaro.org>
Tue, 2 Sep 2014 22:37:11 +0000 (15:37 -0700)
commit3ef9dd2bab7d6a013f75f9fb226d0191e9981288
tree057ff3bdfe0a9df7b759991f529d0cc75da8b82atree | snapshot
parent078a3eb519dacf28cb7c9bb2ad2f62e19ca6dcc2commit | diff
clk: at91: rework PLL rate calculation

The AT91 PLL rate configuration is done by configuring a multiplier/divider
pair.
The previous calculation was over-complicated (and apparently buggy).
Simplify the implementation and add some comments to explain what is done
here.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/at91/clk-pll.c diff | blob | history
Domain: System / Kernel;