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(parent: 789106d) | patch
dt-bindings: clock: Add StarFive JH7110 PLL clock generator
authorXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 16 Mar 2023 03:05:09 +0000 (11:05 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Tue, 28 Mar 2023 03:23:06 +0000 (12:23 +0900)
commit3eec66cc223998cf1eebd4dedeadde0af92fe296
tree194ee55c67536b8029e16b9523c123f0d2949253tree | snapshot
parent789106d6c66b6bd443adeb01fa2e9aa492086a0ecommit | diff
dt-bindings: clock: Add StarFive JH7110 PLL clock generator

Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml [new file with mode: 0644] blob
include/dt-bindings/clock/starfive,jh7110-crg.h diff | blob | history
Domain: System / Kernel;