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(parent: fe2b9b4) | patch
[x86][inline-asm][llvm] accept 'v' constraint
authorMichael Zuckerman <Michael.zuckerman@intel.com>
Mon, 10 Oct 2016 05:48:56 +0000 (05:48 +0000)
committerMichael Zuckerman <Michael.zuckerman@intel.com>
Mon, 10 Oct 2016 05:48:56 +0000 (05:48 +0000)
commit3eeac2d56b0c5753ca8ea457dd3685b4d0e32344
tree3623a00d1be559136e5d4e8a383a174f356a7c5ctree | snapshot
parentfe2b9b4fbf860e3dc7da7705f548bc8d7b6ab9c1commit | diff
[x86][inline-asm][llvm] accept 'v' constraint

Commit in the name of:Coby Tayree
1.'v' constraint for (x86) non-avx arch imitates the already implemented 'x' constraint, i.e. allows XMM{0-15} & YMM{0-15} depending on the apparent arch & mode (32/64).
2.for the avx512 arch it allows [X,Y,Z]MM{0-31} (mode dependent)

This patch applies the needed changes to clang
 clang patch: https://reviews.llvm.org/D25004

Differential Revision: D25005

llvm-svn: 283717
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/inline-asm-avx-v-constraint.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll [new file with mode: 0644] blob
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