dt-bindings: clk: mpfs document msspll dri registers
authorConor Dooley <conor.dooley@microchip.com>
Wed, 13 Apr 2022 07:58:31 +0000 (08:58 +0100)
committerStephen Boyd <sboyd@kernel.org>
Sat, 23 Apr 2022 01:40:11 +0000 (18:40 -0700)
commit3ebb9fdf466a246bb17164b70039dce584a0b959
treeae147fc6ca7cfa2c222db4bc44d9a62ad6be805b
parent2b6190c804238cbdca4e4fbe20304151203a3837
dt-bindings: clk: mpfs document msspll dri registers

As there are two sections of registers that are responsible for clock
configuration on the PolarFire SoC: add the dynamic reconfiguration
interface section to the binding & describe what each of the sections
are used for.

Fixes: 2145bb687e3f ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding")
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220413075835.3354193-5-conor.dooley@microchip.com
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Documentation/devicetree/bindings/clock/microchip,mpfs.yaml