dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache...
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Fri, 18 Aug 2023 13:57:21 +0000 (14:57 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Fri, 1 Sep 2023 16:08:58 +0000 (09:08 -0700)
commit3e7bf4685e42786dc10a57512c8a767947f25c10
tree2ed56085ed67fa7ef429e4177ae807bfee6815f9
parentb79f300c1fd4bd83b1f827c7a0e043fca7aad73c
dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller

Add DT binding documentation for L2 cache controller found on RZ/Five SoC.

The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. The AX45MP core has an L2 cache controller, this patch
describes the L2 cache block.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230818135723.80612-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml [new file with mode: 0644]